IDDT-based Fault Detection and Localization

A portion of a commercial power grid is used in the development of a pair of related power supply transient current (IDDT) fault detection and localization methods. The methods analyze regional signal variations introduced by defects at a set of the power supply ports on the chip under test (CUT). Current fractions are computed using the areas under the IDDT waveforms generated at neighboring orthogonal pairs of supply ports. The current fraction contour curves obtained from an extensive set of simulation experiments across the power grid layout are well approximated by a set of hyperbola curves. The layout position identified by the intersection of a pair of hyperbola curves is used to detect faults. The sensitivity of the method to faults is increased significantly through several calibration procedures. The calibration techniques are designed to reduce signal variations introduced by performance differences and by changes in the probe card and power grid RLC parameters. A closely related fault localization technique is also demonstrated through SPICE simulation experiments. The method is able to predict the location of the fault effect in the power grid layout. Calibration techniques are also applied here as a means of increasing the level of transparency to the silicon substrate from external measurement points.1